Schuyler Eldridge

verilog. Repository for basic (and not so basic) Verilog blocks with high re-use potential

rocket-rocc-examples. Tests for example Rocket Custom Coprocessors

chisel-paradigms. Chisel examples shown for different programming paradigms

zaozi. Experimental Hobby Project of Chisel Ideas

fair-use. Generate YouTube copyright dispute boilerplate

hdl-scripts. Dumping ground for HDL-related scripts I use or find useful

fpga-zynq. Support for Rocket Chip on Zynq FPGAs

cocktails. Cocktail Menu

instance-choice-abis. Repository showing example FIRRTL uses and ABIs for the instance choice FIRRTL feature

ofdm. Chisel Things for OFDM

algorithms. Software engineering practice, algorithms, and data structures

chisel-book. Digital Design with Chisel

chisel-separable. Separable compilation experiments in Chisel

firrtl-torture. Utilities to generate gnarly test cases for a FIRRTL compiler

cocktail-summary.

gitconsensus-test. Test of gitconsensus to manage Chisel Lang governance

cats-sandbox. Scala

riscv-tools. RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

chisel-template.g8. Scala

palette-art. Experiments in color

verilog_tex. Document and example code for introductory (and not so introductory) Verilog

chisel2-base. Base build environment for Chisel projects

riscv-gnu-toolchain. GNU toolchain for RISC-V, including GCC 5.3.0

cbs_radio. CBS Radio Downloader

generator-bootcamp. Generator Bootcamp Material: Learn Chisel the Right Way

riscv-fesvr. RISC-V Frontend Server

chisel-testers2. Repository for chisel3 testers2 open alpha

riscv-isa-sim. Spike, a RISC-V ISA Simulator

rfcs. RFCs for changes to Chisel, FIRRTL, and related projects