Schuyler Eldridge

Bark. Bark is an iOS App which allows you to push custom notifications to your iPhone

llmfit. Hundreds of models & providers. One command to find what runs on your hardware.

llama-swap. Reliable model swapping for any local OpenAI/Anthropic compatible server - llama.cpp, vllm, etc

ClipCascade. ClipCascade is a lightweight utility that automatically syncs the clipboard across devices, no key press required.

dawarich. Your favorite self-hostable alternative to Google Timeline (Google Location History)

Simulacra-and-Simulation. Simulacra and Simulation, 1981, Jean Baudrillard

qmk_cli. A program to help users work with QMK

silverbullet. An open source personal productivity platform built on Markdown, turbo charged with the scripting power of Lua

docker-omada-controller. Docker image to run TP-Link Omada Controller

AdGuardHome. Network-wide ads & trackers blocking DNS server

slang. SystemVerilog compiler and language services

mimalloc. mimalloc is a compact general purpose allocator with excellent performance.

bc. An implementation of the POSIX bc calculator with GNU extensions and dc. Finished.

prjunnamed. [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain

zaozi. A eDSL framework based on Scala and MLIR, focusing on the Hardware design.

meno. Meno is a tool for visualizing hierarchical data, such as synthesized circuit sizes. It can be built into a single, standalone HTML file. Currently, Meno supports hierarchical area reports from Vivado, Genus, and DC, and hierarchical power reports from PrimeTime.

signalflip-js. verilator testbench w/ Javascript using N-API

bazel_rules_hdl. Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

qmk_userspace. Userspace for the open-source QMK keyboard firmware.

pandoc-crossref. Pandoc filter for cross-references

chisel-template. A template project for beginning new Chisel work

crkbd. Corne keyboard, a split keyboard with 3x6 column staggered keys and 3 thumb keys.

sway. i3-compatible Wayland compositor

qmk-keymap. @getreuer's QMK keymap

switchboard. Communication framework for RTL simulation and emulation.

sus-compiler. A new Hardware Design Language that keeps you in the driver's seat

update-circt. Reusable GitHub Action Workflow to update CIRCT in a downstream project

install-circt. Shell

firrtl-mode. Major mode for editing FIRRTL files in Emacs

finamp. An open source Jellyfin music player

gem5. The official repository for the gem5 computer-system architecture simulator.

pandoc. Universal markup converter

amaranth. A modern hardware definition language and toolchain based on Python

systemc. SystemC Reference Implementation

Silice. Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

PipelineC. PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Amethyst. Automatic tiling window manager for macOS à la xmonad.

firrtl-spec. The specification for the FIRRTL language

mlir-hs. Haskell bindings for MLIR

OpenRCT2. An open source re-implementation of RollerCoaster Tycoon 2 🎢

scirt. Scala Circuit IR Tools

passforios. Pass for iOS - an iOS client compatible with Pass command line application.

tensil. Open source machine learning accelerators

Jarvis. Hacking the Jarvis standup desk from fully.com for home automation using an ESP8266 arduino interface

kratos. :crossed_swords: Debuggable hardware generator

hgdb. Hardware generator debugger

awesome-hdl. Hardware Description Languages

rohd. The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

chiselverify. A dynamic verification library for Chisel.

Publish. A static site generator for Swift developers

python-fpga-interchange. Python interface to FPGA interchange format

RISC-V-Single-Cycle-CPU. RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

www.chisel-lang.org. The home of the Chisel3 website

rocket-chip. Rocket Chip Generator

duh-mem. Ⓜ️ DUH memory package

caravan. A caravan equipped with API for creating bus protocols in Chisel with ease.

XiangShan. Open-source high-performance RISC-V processor

NutShell. RISC-V SoC designed by students in UCAS

perf. FIRRTL

hgdb-firrtl. Scala

riscv-sodor. educational microarchitectures for risc-v isa

circt-fuzzer. Generator of random circuits

calyx. Intermediate Language (IL) for Hardware Accelerator Generators

llvm-project. The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

sv2chisel. (System)Verilog to Chisel translator

a2o. Verilog

kaze. An HDL embedded in Rust.

risc-v-getting-started-guide. The official RISC-V getting started guide

degoogle. A huge list of alternatives to Google products. Privacy tips, tricks, and links.

systolic-array. A DSL for Systolic Arrays

a2i. VHDL

skywater-pdk. Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Elastic-Silicon-Interconnect. ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges off-chip and creates high-level APIs using the type data.

circt. Circuit IR Compilers and Tools

essent. high-performance RTL simulator

DFHDL. DFiant HDL (DFHDL): A Mutli-abstraction Hardware Descripition Language and Framework

chisel-arithmetics. Implementation of low-level hardware arithmatic operations in Chisel

singleton-ops. Operations for primitive and String singleton types

tdt4255-chisel-intro. Scala

gramps. Source code for Gramps Genealogical program

jellyfin. The Free Software Media System - Server Backend & API

example-cflush. An example demonstrating how to use cflush (CFLUSH.D.L1) and use FENCE to ensure flush complete

gemmini-rocc-tests. Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

chisel. Chisel: A Modern Hardware Design Language

jellycli. Jellyfin terminal client

bsc. Bluespec Compiler (BSC)

verible. Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

TraceAtlas. C++

processing-module. Chisel Module that Processes Data

chisel-bfm-tester. BFM Tester for Chisel HDL

chiselwatt. A tiny POWER Open ISA soft processor written in Chisel

sv-parser. SystemVerilog parser library fully compliant with IEEE 1800-2017

WbPlumbing. Wishbone plumbing written in Chisel3

OpenDB. Database and Tool Framework for EDA

Ovenbird. A tool for merging the MyHDL workflow with Vivado

Veriutils. Verification Utilities for MyHDL

PHMon. This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).

chisel-single-file. Single-file Chisel design demo

microwatt. A tiny Open POWER ISA softcore written in VHDL 2008

chisel-coverage. A coverage library for Chisel designs

pandoc-include-code. A Pandoc filter for including code from source files

bashblog. A single Bash script to create blogs. Download, run, write, done!

pandoc-pyplot. A Pandoc filter to generate Matplotlib/Plotly figures directly in documents

sbt-microsites. An sbt plugin to create awesome microsites for your project

dirv. This is my first trial project for designing RISC-V in Chisel

LSOracle. IDEA project source files

act. ACT hardware description language and core tools.

MAGICAL. Machine Generated Analog IC Layout

AnalogDetailedRouter. Intel's Analog Detailed Router

esp. Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

alpha-release. Builds, flow and designs for the alpha release

matchlib. SystemC/C++ library of commonly-used hardware functions and components for HLS.

duh. 👾 Design ∪ Hardware

dinocpu. A teaching-focused RISC-V CPU design used at UC Davis

block-inclusivecache-sifive. Scala

SpinalHDL. Scala based HDL

api-generator-sifive. Wake build descriptions of hardware generators

block-pio-sifive. An example of on-boarding a PIO block in with duh and wake

verilator. Verilator open-source SystemVerilog simulator and lint system

vhd2vl. Yacc

cli. CLI for WaveDrom

RISCV-FiveStage. Marginally better than redstone

onnc. Open Neural Network Compiler

wake. The SiFive wake build tool

fusesoc. Package manager and build abstraction tool for FPGA/ASIC development

CHIPS.

fa18-modem. LTE/WiFi/5G-NR SDR Transceiver

ownphotos. Self hosted alternative to Google Photos

ip-contributions. For contributions of Chisel IP to the chisel community.

aes_chisel. Implementation of the Advanced Encryption Standard in Chisel

PyRTL. A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.

diagrammer. Provides dot visualizations of chisel/firrtl circuits

dsptools. A Library of Chisel3 Tools for Digital Signal Processing

chiseltest. The batteries-included testing and formal verification library for Chisel-based RTL designs.

black-parrot. A Linux-capable RISC-V multicore for and by the world

pydgin. A (Py)thon (D)SL for (G)enerating (In)struction set simulators.

pymtl. Python-based hardware modeling framework

amaranth. command-line AURA client

aura. music library REST API

tigervnc. High performance, multi-platform VNC client and server

airsonic. :satellite: :cloud: :notes:Airsonic, a Free and Open Source community driven media server (fork of Subsonic and Libresonic)

hwacha. Microarchitecture implementation of the decoupled vector-fetch accelerator

cascade. A Just-In-Time Compiler for Verilog from VMware Research

uclid. UCLID5: formal modeling, verification, and synthesis of computational systems

soDLA. Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

SYMPL-GP-GPU-Compute-Engines. Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.

trainwreck. Original RISC-V 1.0 implementation. Not supported.

midas. FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

MinecraftHDL. A Verilog synthesis flow for Minecraft redstone circuits

klayout. KLayout Main Sources

dblclockfft. A configurable C++ generator of pipelined Verilog FFT cores

math-as-code. a cheat-sheet for mathematical notation in code form

openpiton. The OpenPiton Platform

pipeproof. PipeProof

vtr-verilog-to-routing. Verilog to Routing -- Open Source CAD Flow for FPGA Research

microprobe. Microprobe: Microbenchmark generation framework

bottlerocket. Scala

riscv-qemu. QEMU with RISC-V (RV64G, RV32G) Emulation Support

firrtl. Haskell FIRRTL implementation

grift. Galois RISC-V ISA Formal Tools

firrtl-interpreter. A scala based simulator for circuits described by a LoFirrtl file

vunit. VUnit is a unit testing framework for VHDL/SystemVerilog

Halide. a language for fast, portable data-parallel computation

coreir. C++

fft. Scala

magma. magma circuits

spatial. Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

snorkel. A system for quickly generating training data with weak supervision

Charm. A Language for Closed-form High-level ARchitecture Modeling

Delite. The Delite Git Repo

riffa. The RIFFA development repository

hammer. Hammer: Highly Agile Masks Made Effortlessly from RTL

devsim. TCAD Semiconductor Device Simulator

Pyverilog. Python-based Hardware Design Processing Toolkit for Verilog HDL

treadle. Chisel/Firrtl execution engine

ghdl. VHDL 2008/93/87 simulator

firrtlator. firrtlator is a FIRRTL C++ library

chisel-testers. Provides various testers for chisel users

chisel-bootcamp. Generator Bootcamp Material: Learn Chisel the Right Way

firrtl. Flexible Intermediate Representation for RTL

visualizer. Provides dot visualizations of chisel/firrtl circuites

riscv-semantics. A formal semantics of the RISC-V ISA in Haskell

bnn-fpga. Binarized Convolutional Neural Networks on Software-Programmable FPGAs (FPGA'17)

firrtl-syntax. Vim syntax highlighting for Firrtl files

OpenTPU. A open source reimplementation of Google's Tensor Processing Unit (TPU).

riscv-formal. RISC-V Formal Verification Framework

fpgamake. Generates Makefiles to synthesize, place, and route verilog using Vivado

l3riscv. An executable specification of the RISCV ISA in L3.

rv8. RISC-V simulator for x86-64

spatial-lang. Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

chisel-utils. A library of modules for Chisel

MachSuite. Benchmarks for Accelerator Design and Customized Architectures

chipyard. An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

fathom. Reference workloads for modern deep learning methods.

parallella-riscv. RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards

chisel-examples. Chisel examples and code snippets

chisel-book. Digital Design with Chisel

chisualizer. Block-diagram style digital logic visualizer

chisel3-skeleton. Scala

dsp-chisel3. Playground for ChiselDSP port to chisel3