fermarsan

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@fermarsan

aixt. Microcontrollers programming framework based on Vlang.

90

quarto-kroki. Quarto extension for rendering Kroki diagrams on HTML and PDF documents.

1

veri2sim. This is a simple Verilog to SimulIDE block converter written in Python using the PLY module.

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vly. VLY will be a port of PLY / SLY parser on Vlang

1

submodules_in_Vlang. This repository is for testing the definition and working of submodules in Vlang.

1

template_example_vlang. This repository is for testing of text template usage in Vlang.

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