zhenwei

nvdla-attn-mechanism. Hardware acceleration for transformer attention mechanisms on NVIDIA Deep Learning Accelerator (NVDLA), enabling efficient inference of transformer models with 135× better power efficiency than CPU implementations.

ai-core-notes.

os-workbench. jyy os enhanced

open-ysyx. ysyx 开源项目管理委员会

fpga-npu. SystemVerilog

Nanhu-V1. write xiangshan nanhu from scratch

CS106X. abstract program in c++

ca_perf_model_lab. C++

oscpu-framework. A Verilator-based demo.

ridecore. RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

practice-notes. learning in pcl

llama2-tutorial. Cuda

TF-Keras-Notes. Jupyter Notebook

camodel-demo. C++

py-v. A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.

python. 机器学习

npu-playground. Python

vortex-warp-cooperative-tcore. Verilog

chiplab. Assembly

systemc-playground. C++

SoomRV-difftest. SoomRV with difftest

GEM5. C++

trace-sim.

Gemmini_doc. 关于移植模型至gemmini的文档

spike-flexicas. C

SMARTsim. C

nemu-riscv64. The wrapper repo for NJU ICS PA.

RISC-Core-on-FPGA-Arch2021. A course project for Computer Architecture Course at ZJU.

ppc750sim. C

llama2.c. Inference Llama 2 in one file of pure C

sim-godson. C

cache-simulator. C++