dillonhuff

ahaHLS. An open source high level synthesis (HLS) tool built on top of LLVM

gpr. A simple C++ G-code parser

clockwork. A polyhedral compiler for hardware accelerators

stl_parser. A simple parser for binary .stl files

scg. 3D Computational Geometry in C++11

TinyCPU. Educational Verilog CPU Implementations of a Tiny Instruction Set

Folly. First order logic in Haskell

bsim. C++

VerilogToCoreIR. Experimenting with yosys verilog frontend to coreir

SFGen. A Python HLS Tool For Generating Special Functions (Divide, Square Root, etc.)

gca. A process planner for 3-axis CNC mills

arena_allocator. A C++ Header Only Arena Allocator

MagmaFPGA. From the recent magmathon

CGRA_verilog_mirror. Mirror of CGRA verilog generation on kiwi

CGRA_partial_eval. Verilog

Proper. Propositional logic theorem prover in Haskell

gmeans. C++

ncsim_cgra_test. Verilog

DifferenceLogic. A theory solver for difference logic

CoreIRBenchmarks. A collection of larger designs to test coreir with

axi_rtl_demo. Example implementation of AXI in Verilog.

pwmatrix. Python

dpgen. Python

vivado_designs. Verilog

SpecCircuit. RTL Simulator with Runtime Circuit Specialization

Halide-HLS. For the Aetherling PLDI paper

units_library_talk. FlashG About Units of Measurement

vivado_synth. Simple vivado synthesis script as reminder

PySystolicArray. Python model of systolic array

func_test. __func__ vs __PRETTY_FUNCTION__

coreJIT. C++

CoreRiscV. Verilog

stam_fluid. C++ version of Jos Stam simple fluid solver for games

watertight. Simple watertight mesh tools

mini-cmake-qt-vtk-cgal. C++

CGRAGenerator. Python

IntLang. A very simple compiled functional language

RQE. Haskell

LambdaCalculus. Haskell interpreter for lambda calculus