This is your work, valued

Sunnyvale, CA

Tom Verbeure

Elite
@tomverbeure

24/7 electronics (and some biking)

panologic-g2. Pano Logic G2 Reverse Engineering Project

153

rt. A Full Hardware Real-Time Ray-Tracer

116

math. SpinalHDL Hardware Math Library

102

fake_parallel_printer. Capture traffic on parallel printer port to USB

94

kv260_bringup. Temporary repo to gather information about the Kria KV260 board

83

panologic. PanoLogic Zero Client G1 reverse engineering info

77

mr1. MR1 formally verified RISC-V CPU

59

tomverbeure.github.io. HTML

51

cxxrtl_eval. Experiments with Yosys cxxrtl backend

50

cisco-hwic-3g-cdma. Reverse Engineering of the Cisco HWIC-3G-CDMA PCB

46

gdbwave. GDB server to debug CPU simulation waveform traces

43

bscan_tools. Various JTAG boundary scan tools

37

ecp5_jtag. Use ECP5 JTAG port to interact with user design

33

color3. Information about eeColor Color3 HDMI FPGA board

27

vexriscv_ocd_blog. Repo that shows how to use the VexRiscv with OpenOCD and semihosting.

26

aha363. Python

25

jtag_uart_example. Mini CPU design with JTAG UART support

21

pdm. Assembly

21

upduino. Verilog

20

usb_system. SpinalHDL USB system for the ULPI based Arrow DECA board

20

intel_jtag_uart. A Python module to interact with an Intel JTAG UART

17

intel_jtag_primitive_blog. How to use the Intel JTAG primitive without using virtual JTAG

17

fpga_quick_ram_update. Quickly update a bitstream with new RAM contents

17

arrow_deca. LED blink example design for the Arrow DECA FPGA board

16

yosys_gatemap. An example that shows how to map a design to a custom cell library.

16

cube. Scala

15

sidechan. Side channel communication test within an FPGA

11

spdif_pmod. S/PDIF Output PMOD

9

rv32soc. Verilog

9

cisco-vwic3-2mft.

9

vga_i2c. VGA I2C GPIO + Atari 2600 Joystick Extender

8

gps_interposer. C++

8

jtag_gpios. Tutorial on how to integrate custom JTAG functionality into existing tools

8

multi_port_mem. Implementing multi-port memories in FPGAs

7

uart2jtag_uart. Small project to connect UART pins to JTAG UART

7

usb_pmod.

6

dsp_guide. Jupyter Notebook

6

cpu_skeleton. Basic skeleton for an embedded Vexriscv CPU system.

5

logic_analyzer. Verilog

5

led_matrix. Scala

4

galois. Python

4

yosys. Yosys Open SYnthesis Suite

3

Pano-Logic-Zero-Client-G2-FPGA-Demo. Constraints file and Verilog demo code for the Pano Logic Zero Client G2

3

chubby75. Linsn RV901T HUB75 LED "Receiver Card" Reverse Engineering

3

yosys_split_ops. Yosys techmaps to split operations on large vectors into multiple smaller ones.

3

UPduino-v2.1. UPduino

3

yosys_techmap_blog. Example repo for blog post

3

kicad_personal. Personal library with KiCAD components

3

max10_devkit_blinky. Tcl

2

siglent_remote_blog. Collection of remote control scripts for Siglent oscilloscope

2

picorv32. PicoRV32 - A Size-Optimized RISC-V CPU

2

arrow_deca_pmod_cape.

2

blinky. Example LED blinking project for your FPGA dev board of choice

2

ball. LED bal

2

Cores-VeeR-EH1-tvb. VeeR EH1 core

1

Formal_Advanced_State. An example of running formal from an advanced state with Yosys

1

bangbangbadge.

1

parametric_case.

1

tang_primer_20k. GLSL

1