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24/7 electronics (and some biking)
panologic-g2. Pano Logic G2 Reverse Engineering Project
153rt. A Full Hardware Real-Time Ray-Tracer
116math. SpinalHDL Hardware Math Library
102fake_parallel_printer. Capture traffic on parallel printer port to USB
94kv260_bringup. Temporary repo to gather information about the Kria KV260 board
83panologic. PanoLogic Zero Client G1 reverse engineering info
77mr1. MR1 formally verified RISC-V CPU
59tomverbeure.github.io. HTML
51cxxrtl_eval. Experiments with Yosys cxxrtl backend
50cisco-hwic-3g-cdma. Reverse Engineering of the Cisco HWIC-3G-CDMA PCB
46gdbwave. GDB server to debug CPU simulation waveform traces
43bscan_tools. Various JTAG boundary scan tools
37ecp5_jtag. Use ECP5 JTAG port to interact with user design
33color3. Information about eeColor Color3 HDMI FPGA board
27vexriscv_ocd_blog. Repo that shows how to use the VexRiscv with OpenOCD and semihosting.
26aha363. Python
25jtag_uart_example. Mini CPU design with JTAG UART support
21pdm. Assembly
21upduino. Verilog
20usb_system. SpinalHDL USB system for the ULPI based Arrow DECA board
20intel_jtag_uart. A Python module to interact with an Intel JTAG UART
17intel_jtag_primitive_blog. How to use the Intel JTAG primitive without using virtual JTAG
17fpga_quick_ram_update. Quickly update a bitstream with new RAM contents
17arrow_deca. LED blink example design for the Arrow DECA FPGA board
16yosys_gatemap. An example that shows how to map a design to a custom cell library.
16cube. Scala
15sidechan. Side channel communication test within an FPGA
11spdif_pmod. S/PDIF Output PMOD
9rv32soc. Verilog
9cisco-vwic3-2mft.
9vga_i2c. VGA I2C GPIO + Atari 2600 Joystick Extender
8gps_interposer. C++
8jtag_gpios. Tutorial on how to integrate custom JTAG functionality into existing tools
8multi_port_mem. Implementing multi-port memories in FPGAs
7uart2jtag_uart. Small project to connect UART pins to JTAG UART
7usb_pmod.
6dsp_guide. Jupyter Notebook
6cpu_skeleton. Basic skeleton for an embedded Vexriscv CPU system.
5logic_analyzer. Verilog
5led_matrix. Scala
4galois. Python
4yosys. Yosys Open SYnthesis Suite
3Pano-Logic-Zero-Client-G2-FPGA-Demo. Constraints file and Verilog demo code for the Pano Logic Zero Client G2
3chubby75. Linsn RV901T HUB75 LED "Receiver Card" Reverse Engineering
3yosys_split_ops. Yosys techmaps to split operations on large vectors into multiple smaller ones.
3UPduino-v2.1. UPduino
3yosys_techmap_blog. Example repo for blog post
3kicad_personal. Personal library with KiCAD components
3max10_devkit_blinky. Tcl
2siglent_remote_blog. Collection of remote control scripts for Siglent oscilloscope
2picorv32. PicoRV32 - A Size-Optimized RISC-V CPU
2arrow_deca_pmod_cape.
2blinky. Example LED blinking project for your FPGA dev board of choice
2ball. LED bal
2Cores-VeeR-EH1-tvb. VeeR EH1 core
1Formal_Advanced_State. An example of running formal from an advanced state with Yosys
1bangbangbadge.
1parametric_case.
1tang_primer_20k. GLSL
1