Julia Desmazes

Nasdaq-HFT-FPGA. RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.

low-latency-ethernet. RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

Systolic_MAC_with_DFT. GF180 ASIC tapeout of a 2x2 MAC with DFT infrastructure

Systolic_Array_with_DFT_v2. IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator taped out on GF180.

ethernet-physical-layer. RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

Until_Heat_Death_Do_Us_Part. Counting until the heat death of the universe, and broadcasting the counter every second over 100Mbps ethernet.

BFloat16. RTL implementation of a performance/area optimized bfloat16 adder and multiplication.

blake2_asic. SKY130A implementatoin of the Blake2s hash algorithm

stm32h750-dev-board. Small embedded dev board with an STM32H7 and a full J-link connector

uselessly_fast_bfloat16_multiplier. Pushing the bf16 multiplication clock frequency to the max on the nominal corner on IHP 130nm 5L node.

MoldUPD64. RTL implementation of a MoldUPD64 receiver.

AES. RTL implementaion of 128 bit Advanced Encryption Standard (AES) encyption algorithm

ITCH. RTL implementation of the Nasdaq ITCH protocol decoder.

Teapot. 100Mbps Ethernet accelerator wrapper.

tcp. RTL implementation of the a single socket TCP client

NASDAQ_server_C_lib. Fake nasdaq server C library used in testing FPGA HFT project

OUCH_5.0_C_lib. Nasdaq OUCH 5.0 C libary

Blake2. Blake2 RTL implementation

rtl_utils. Collection of rtl tricks

tt_gf_ocd_sram_test. Tiny tapeout gf180 ocd sram test for the gf0p3 shuttle

ethernet_switch_asic. Open source sillicon for a 100Mbps unmanaged cut-through ethernet switch.

ethernet_packet_C_lib. C library for creating network packages, wireshark compatible, primarily for testing network layer RTL.

CRC_generator. CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible. Written by Evgeni Stavinov.

Expresso_ASIC_Chip. Full chip tapeout of the unmanaged cut-through 100Mbps Ethernet switch and the Heat Death of the Universe beacon. Targeting 0.5x0.5 waffer.space run#2.

CAM. Content Addressable Memory Experimentations

utils_C_lib. Generic C FIFO library.

TOTEM_backlight. TOTEM keyboard variant with backlight for the wired version and re-worked for outsourcing assembly.

Zeldy_MCU. C

Zeldy. Zeldy is a power monitoring system.

Zeldy_HW. AGS Script

GHDL-Hello-World. Simple GHDL example with makefile

TotalView_ITCH_5.0_C_lib. Small C library to handle itch messages

VPI_utils_C_lib. VPI utils C lib, used for interfacing with iverilog and verilator VPI interface.

Zeldy_Server.

openocd_ultrascale_plus. OpenOCD fork, working on improving Xiling UltraScale+ support

SoupBinTCP. RTL implementation of SoupBinTCP version 3.0

essenceia.github.io. Portfolio website

Nasdaq_binaryfile_utils. C

formal_experiements. Formal verification experiments

DFT_FPGA_Emulation. DFT scan chain emulation on FPGA.

analog_sky26a. Analog experiements, targetting sky26a, double oscillators

namibj. Python

Expresso_ASIC_Chip_0p5x1_slot. 0p5x1 ws slot for the expresso ASIC chip

Expresso_ASIC_Chip_1x1_slot. Python