Tingyuan LIANG

Basic-SIMD-Processor-Verilog-Tutorial. Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

AMF-Placer. AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

LLVM-9.0-Learner-Tutorial. A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it.

Light-HLS. Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)

PAAS_V1.0. PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems

Multi-User-Transmit-Beamforming-Linear-Regression-Convex-Optimization-Tutorial. In this work, we use convex optimization package in MATLAB to implement multi-user transmit beamforming problem and linear regression. This is the homework 2 of ELEC 5470 Convex Optimization, HKUST.

Hi-DMM. Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)

Zynq_HLS_DDR_Dataflow_kernel_2mm. This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation

AutoCellLibX. AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining

LLVM-11-Tutorials. A blog for LLVM(v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM.

FPGA. Recipe for FPGA cooking

High-Performance-Karatsuba-Multiplier-HLS-FPGA. Implement High-Performance Karatsuba Multiplier in High-Level Synthesis (HLS) for FPGA Based on Recursive Template

KMeans-Emails-Clustering-Visualization-NLP. KMeans-Emails-Clustering-Visualization-NLP: KMeans is used to cluster the emails. The words in the contents of emails are tokenlized and stemmed. This project transforms the corpus into vector space using tf-idf.By multidimensional scaling, the clustering result is visualized.

Zedboard_Intergrating_HLS_IP_AND_DDR. This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.

Barrier-Method-LASSO. This project, based on MATLAB, is an implementation of barrier method to solve LASSO problem. The barrier method is designed with centering step based on newton method.

Zynq_HLS_DDR_AXI_IPs_Multiple_Clock. VHDL

Zedboard-xfOpenCV-Optical-Flow. xfOpenCV Optical Flow implemented on Zedboard with built aarch32 OpenCV libraries

Staublis_Computer_Vision_Course_Project. It is a course project finished during ELEC 5640 Robot Manipulation. The mission of the project has been described in the report. The coding is .... quite rough but it may help other to deal with staublis and CV. The report is very detailed and hope it helps. Please be careful of the robot arm and don't hurt yourself and others.

TCP-IPv6-OpenCV-Video-Streaming. Implement OpenCV video streaming based on TCP/IPv6

google-ngrams-2020updated. Python scripts updated in 2020 for retrieving CSV data from the Google Ngram Viewer and plotting it in XKCD style. The Python script for retrieving ngram data was originally modified from the script at www.culturomics.org.

gem5-HDL_v1.0. gem5-HDL_v1.0

Verilog-UART. 3个独立组件：UART接收器、UART发送器、UART交互式调试器

HLS. Vitis HLS LLVM source code and examples

hkust-latex-thesis. A Better HKUST LaTeX Thesis Template

cva6. The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

HLS_designs. Systolic array implementations for Cholesky, LU, and QR decomposition

google-ngrams. Python scripts for retrieving CSV data from the Google Ngram Viewer and plotting it in XKCD style. The Python script for retrieving ngram data was originally modified from the script at www.culturomics.org.

Hi-ClockFlow. Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis

Tensorflow_Customized_Optimizer_Tutorial. A previous project based on tensorflow in COMP 5212, HKUST. The project includes user-customized momentum SGD optimizer, CNN and CAE (convolutional autoencoder).

vivado-library. C

corundum. Open source, high performance, FPGA-based NIC

HLS-Tiny-Tutorials. C

riscv-boom. SonicBOOM: The Berkeley Out-of-Order Machine

EDA-wiki. EDA wiki

XilinxTclStore. Xilinx Tcl Store

NAGC. Non-Linear Attributed Graph Clustering by Symmetric NMF with PU Learning

astran. ASTRAN - Automatic Synthesis of Transistor Networks

lemberg. Lemberg is a time-predictable VLIW processor optimized for performance.

ELAS_SoC. Source Code for "Real-Time Dense Stereo Matching with ELAS on FPGA Accelerated Embedded Devices"

HLS-Cryptography-Accelerator. A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer

RapidWright. Build Customized FPGA Implementations for Vivado

rsd. RSD: RISC-V Out-of-Order Superscalar Processor

riscv-cores-list. RISC-V Cores, SoC platforms and SoCs

OpenCGRA. OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

vsdstdcelldesign. This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.

16-720B-Computer-Vision. 16-720B Computer Vision (Fall 2018) at Carnegie Mellon University

f4pga. FOSS Flow For FPGA

zybo_petalinux. Small projects intended to run on the Digilent Zybo development board, utilizing PetaLinux on the Zynq's ARM processor.

HLS_BLSTM. The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))

bsg_manycore. Tile based architecture designed for computing efficiency, scalability and generality

hdl. HDL libraries and projects

LLVM-9-for-Light-HLS. LLVM-9 with arbitrary precision integer patch for Light-HLS

Summary-Notes-for-Machine-Learning-COMP5212. Summary Notes for Machine Learning (COMP5212), which might help to review what have learned from the course

zynqnet. Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"