Stafford Horne

sdram-controller. Verilog SDRAM memory controller

uart. Verilog uart receiver and transmitter modules for De0 Nano

adc_interface. Verilog ADC interface for adc128s022 found in De0 Nano

gcc. GCC port rewrite for OpenRISC

kicad-spice-demo. Demo of simulating kicad schematics in spice

tls-examples. TLS access example code snippets

ac97. opencores ac97 controller verilog core

intelhex. Intel HEX file generator

mor1kx-generic. mor1kx OpenRISC generic test harness support verilator and iverilog

cgen. architecture code generation used by binutils

wb_dma. Wishbone dma/bridge controller in verily

or1k-toolchain-build. OpenRISC toolchain build scripts

ompic. Open Multi-Processor Interrupt Controller - for OpenRISC

or1k-utils. linux initramfs, testing, openocd, and other random utils for openrisc

berkeley-softfloat-2. Berkeley Softfloat 2c - with updates

de0_nano-multicore. OpenRISC multicore SoC for De0 Nano

adc_preamp. Kicad schematic for opamp based microphone preamp circuit used with my adc_interface project

hostconfig. My backup of host and dot file config

or1k_marocchino. OpenRISC processor IP core based on Tomasulo algorithm

de0_nano. Verilog

stffrdhrn.github.io. Github blog for stafford horne

de0_nano. OpenRISC SOC for the De0 Nano FPGA dev board

fudosan. PHP, Twiiter Bootstrap, jQuery, CouchDB based webapp for managing real-estate property and client relationships

serv. SERV - The SErial RISC-V CPU

digi-recorder. A digital recorder for fpga in verilog, tested on de0 nano.

wb_sdram_ctrl. SDRAM controller with multiple wishbone slave ports

or1k-rootfs-build. Build tools to make openrisc platform rootfs images

binutils-gdb. Binutils and gdb fork for OpenRISC

micron-cores. FuseSOC cores for micron verilog models

junk. Dumping ground for test programs and ideas, mostly used for toolchain testing

HDMI2USB-litex-firmware. A version of the HDMI2USB firmware based around LiteX tools produced by @Enjoy-Digital (based on misoc+migen created by @M-Labs)

boards. Various PCB designs in KiCad

mor1kx. mor1kx - an OpenRISC 1000 processor IP core

freemodelfoundry-cores. FuseSOC cores for free model foundry verilog models

dram_tester. A testsuite for my dram controller

openrisc.github.io. HTML

linux. Linux kernel source tree

jtag_vpi. TCP/IP controlled VPI JTAG Interface.

verilator_tb_utils. Verilator test bench utils

librecores-pipeline-lib. Jenkins Pipeline library for LibreCores CI

fusesoc-cores. FuseSoC standard core library

wb_streamer. Wishbone component for converting data streams to wishbone transactions

wiredelay. A wire delay simulation verilog core

adv_dbg_if. Universal Advanced JTAG Debug Interface

openocd. Spen's Official OpenOCD Mirror

wb_bfm. Wishbone Bus Functional Model

edalize. An abstraction library for interfacing EDA tools

musl-cross-make. Simple makefile-based build for musl cross compiler

intgen. An verilog core for testing CPU interrupts

tutorials. OpenRISC Tutorials