Meinhard Kissich

FazyRV. A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

RV32I_SC_Logisim. A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

SimIO. SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.

logIP. Logic Analyzer IP Core

tt06-FazyRV-ExoTiny. SystemVerilog

smsbox. This fun project receives text messages (sms) and prints them via the thermal printer

FazyRV-ExoTiny. Assembly

Nokia_5110_Design_Clock. [WIP] A little project using a Nokia 5110 display and an Arduino Nano + DS3231 RTC to build a neat clock.

Checkr. A minimalistic UI for grammar correction with self-hosted AI.

Streamliner. Python

GameGrid64. GameGrid64 is a 64x64 LED Matrix gaming console that was created as a weekend project.

hazard3-sim. Summary on how to debug code for the Hazard3 core in simulation.