Iztok Jeras

rp32. RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

sockit_owm. SocKit 1-wire (onewire) master

fpga-hdl. A set of small Verilog projects, to simulate and implement on FPGA development boards

TCB. Tightly Coupled Bus, low complexity, high performance system bus.

HDLDB. GDB server stub for replaying recorded HDL simulations

soc-kit. System on Chip toolkit (Verilog 2001)

synthesis-primitives. Observing and optimizing synthesis of common bit manipulation operations for FPGA and ASIC

SystemC-UVM. UVM-SystemC Library

sockit_cdc. clock domain crossing FIFO

rp8. RISC processor 8bit (AVR ISA), RTL based on 'navre'

riscv_asm_sv. RISC-V assembler/dis-assembler written in SystemVerilog

sockit_spi. SocKit SPI (3-wire, dual, quad) master

butterflylogic. Verilog

vivado_simulator. Evaluation of the Xilinx Vivado simulator

SystemVerilog-tests. Tests for a set of SystemVerilog features over a set of simulation and synthesis tools.

ADAMS. all digital PLL

preimages-2D. 2D cellular automata preimages count&list algorithm

SystemC-Verification. SystemC Verification Library (SCV)

verilog_coding_style. Verilog coding style examples

Terasic_DE1. Demo designs for the Terasic DE1 board

ivtest. Regression test suite for Icarus Verilog.

zephyr-qemu-test-app. Zephyr QEMU test app

webgl-quad-ca. WebGL QUAD CA sumulator

sigrok-dump. Example sigrok dumps

sigrok. sigrok

iverilog. Icarus Verilog

ecs8. projects related to the ECS8 board

office. LibreOffice templates

sockit_i2c. I2C master/slave RTL and bench model code