Jamie Iles

80x86. 80186 compatible SystemVerilog CPU core and FPGA reference design

uart. Verilog UART

oldland-cpu. Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

rpi-gdb. Raspberry Pi GDB remote serial protocol stub

fpga-cmake. Building FPGAs with Quartus+CMake

oldland-sdram. SDR SDRAM controller

a5-1-wb-macro. A5/1 Wishbone macro for Caravel ZeroToAsic group submission

qemu-picoxcell. qemu port for picoxcell

linux-picoxcell. Picochip picoXcell kernel tree

rxv. RXV RISC-V soft core

riscv-compliance. C

riscv-tests. C

multi_project_tools. Python

verilator. Verilator open-source SystemVerilog simulator and lint system

u-boot-oldland. u-boot port for the Oldland CPU