gatecat

RFToolSDR. AD9361 based USB3 SDR

DSITx. MIPI DSI transmitter core for Xilinx FPGAs (work in progress)

openMixR. 4k Mixed Reality headset

up5k-demos. ice40 UltraPlus demos

ElasticC. lightweight open HLS for FPGA rapid prototyping

prjtrellis-dvi. DVI video out example for prjtrellis

TinyTracker. Tiny LoRa-based GPS tracker for balloon experiments

hilotof. HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs

LoRaExperiments. Miscellaneous Experiments with LoRa

nextpnr. nextpnr portable FPGA place and route tool

ulx3s. Verilog

pmods. PMODs primarily for demo usage with icestorm

flow-examples. Misc open FPGA flow examples

ecp5-hat. SoC hat for ECP5 Versa & EVN boards

yoloRISC. porting lowRISC to yosys/nextpnr/trellis on the Lattice ECP5 fpga

picorv32. PicoRV32 - A Size-Optimized RISC-V CPU

IcySprites. The easiest to use sprite-based graphics kit for FPGAs

icestorm. Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

LoRaPP. Small but flexible LoRa module. 434/868MHz; optional PA, LNA and SAW

linux-on-litex-vexriscv. Experiments with Linux on LiteX-VexRiscv

FPGALab2016. 2016 Imperial FPGA Lab

yosys. Yosys Open SYnthesis Suite

wb_sdram_ctrl. SDRAM controller with multiple wishbone slave ports

icestorm-fpl. Icestorm workshop at FPL 2019

kendryte-doc-ds. Kendryte datasheet

micropython-icevision. MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems

arachne-pnr. Place and route tool for FPGAs

prjuray. Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

tiler_rotate_shim. OMAP5 OpenGL rotation shim for Pyra

TinyFPGA-B-Series. Open source design files for the TinyFPGA B-Series boards.

tinyfpga-soc. TinyFPGA SoC using lm32 CPU

migen. A Python toolbox for building complex digital hardware

formal-fpl. Verilog