Chili.CHIPS

wireguard-fpga. Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

openCologne. Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

openeye-CamSI. A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

openPCIE. Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource on the Host side too. Our project roots for the Root Port in 4 ways: |1|openRTL |2|openBFM with unique SIM setup, way faster than vendor's |3|openSW stack |4|one-of-a-kind open backplane.

openCologne-PCIE. The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog RTL with best-in-class VIP, M.2 and Edge cards for GateMate. Project opens PCIE connectivity to FPGAs, ASICs, I/O, acceleration, AI...

openXC7-TetriSaraj. Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

uberClock. Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numerical sauce. The best of all is that the sauce is not secret, but fully open to the public.

openeye-CamSI-ethernet. 1GigE UDP uplink of the live, real-time camera video stream. Think of it as Webcam-over-Ethernet, or RemoteCam. Great for security apps, this is a component of our 'openeye-CamSI' project that may also be used independently. It is fully operational and open for porting to your projects. Enjoy!

openENOC. The first-ever opensource Ethernet-based Network-On-Chip (NOC) | Scalable, modular, interoperable, ubiquitous | Many-to-many frame-switched interconnect for CPUs, peripherals, acceleration cores...

tango-with-pango. Playground for PangoMicro FPGAs.