Ben Reynwar

fft-dit-fpga. Verilog module for calculation of FFT.

pyvivado. Python tools for Vivado Projects

wiktionary-parser. A parser and autocorrection tool for wiktionary.

htfft. A high throughput FFT implementation

fpga-sdrlib. Verilog modules for software-defined radio.

slvcodec. Generate conversions to/from VHDL types and std_logic_vector. Generate python-based tests.

axilent. Python to AXI4

rfgnocchi. Library of HDL signal-processing blocks for use with RFNoC

gnuradio-old. gnuradio

fusesoc_generators. Add generators to fusesoc so that depenedencies can be generated from generic parameters.

gr-ham. Python

202008_cocotb_presentation. Verilog

verilate. Running python tests with verilator

SiLemma. Trying to prove things about circuits in Dafny

zamlet. Scalable RISC-V Vector Processing Unit

scvivado. Scala tools for Vivado (Not useful yet. Learning Scala)

check_cocotb_ghdl. Just a check to make sure cocotb and ghdl are working together

loos_sasa. C++

veifa. JavaScript