signalflip-js. verilator testbench w/ Javascript using N-API
19reciprocal-sv. Fixed point reciprocal in SystemVerilog
7elastic-buffer. buffers for valid-ready designs
5leading-zeroes-counter. Leading zeroes counter (SystemVerilog)
4eth-uvm. SystemVerilog
3spinal-interfaces. interfaces such as jtag, apb, and others in SpinalHDL
2de0-nano-projects. de0 nano projects
2mpw3-nco. NCO on mpw3 (group submission)
2vpiexamples. vpi (verilog pli) exmaples
2basic-signalflip-example. Signalflip example: simulate counter rtl
2riscv-sv. RISC-V implementation
1lfsrLED-board. 555 timer and shift register chip use to create led light up pattern
1DSP-STM32. DSP projects on STM32F429ZI Nucleo board
1two-input-arbiter. Two input arbiter
1APB3-config-regs. Implements two config registers with APB3 interface. Verification testbench done in verilator using signalflip-js
1DSP-C. DSP functions in C++/C
1i2s-mpw7. Verilog
1ldpc_ccsds. LDPC CCSDS octave
1sva_examples. symbiyosys sva exaples
1MCUBoard. STM32F104 board with LEDs
1tun2udp. tun to udp python script
1InternetClock. Clock display using 4DGL-uLCD-SE, Ethernet, and LPC1768 (mbed)
1usb_uart_tinybx. working usb uart on tinyfpga bx
1fp_reciprocal. Fixed point implementation of reciprocal (described in JS but can be easily ported to verilog)
1ulcdAccel-demo. 4DGL-uLCD-SE with accelerometer project on LPC1768. Ball moves with accelerometer vector.
1fixed2float. Convert fixed point to float and vice-versa
1fsvcpp-spec. fsvcpp
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