Adilson Dias
Senior Systems Engineer | C++ | FPGA | Custom 10GBASE-R PHY | Hardware/Software Co-Design | AMD/Xilinx Certified
fpga-trading-systems. Production-grade low-latency FPGA trading system. Features custom VHDL 10GBASE-R PHY, hardware NASDAQ ITCH 5.0 order book, C++ DPDK/XDP kernel bypass, and PCIe DMA acceleration. LLM-Inference
6621-fpga-pcie-gpu-bridge. FPGA PCIe bridge to GPU - High-bandwidth interface for FPGA-GPU communication
3FMRADIO-STC15W. FM RADIO on STC15W
131-10gbe-uart-debug. This project integrates the ALINX 10GbE UDP vendor design with a UART debug interface for monitoring network traffic and system status. It serves as the foundation for ITCH market data reception on the AX7325B (Kintex-7 XC7K325T) FPGA.
116-cpp-order-execution. Order execution engine with FIX 4.2 protocol - Price-time priority matching, LMAX Disruptor ring buffers for IPC, ~2μs order-to-fill round-trip latency.
134-fpga-tcp-itch-parser. Implements multi-protocol market data parsing supporting NASDAQ (UDP/MoldUDP64), ASX (TCP/SoupBinTCP), and B3 Brazilian Exchange (UDP/SBE) market data feeds. Integrates with Project 33's 10GBASE-R PHY for 10GbE reception and outputs parsed messages via Aurora to FPGA2 (order book engine).
133-fpga-10gbe-phy-custom. A complete custom implementation of the 10GBASE-R Physical Layer (PHY) in VHDL. This implementation provides full control over the 10 Gigabit Ethernet physical layer without relying on encrypted vendor IP.
1ESP32-Smart-Garage-Door_Controller. Garage Door controller
1