Michael A. Morris

MAM65C02-Processor-Core. Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001)

Booth_Multipliers. Parameterized Booth Multiplier in Verilog 2001

1PPS-DPLL. DPLL for phase-locking to 1PPS signal

M65C02A. Enhanced 6502/65C02 Microprogrammed FPGA Processor Core (Verilog-2001)

MiniCPU-S. Minimal FPGA Processor Core for Stack-based CPU for CPLDs Using Bit-Serial Architecture

MiniCPU. Minimal FPGA Processor Core for anycpu.org 8-bit Challenge

PIC16C5x. PIC16C5x-compatible FPGA Processor Core (Verilog-2001)

Mak-Pascal. Recursive Descent Pascal Compiler for M65C02A and i8086

M16C5x. Soft-Microcomputer using PIC16C5x-compatible FPGA Processor Core (Verilog-2001)

verilog-6502. A Verilog HDL model of the MOS 6502 CPU

RTFIFO. Microprogrammed Receive/Transmit Block RAM FIFO for UARTs or similar devices

PLATool. Programmable Logic Array (PLA) Tool - Converts ROMs into CPLD equations. (Python 3)

Chameleon. Arduino-compatible FPGA Shield Board

MultiUART. Multi-Channel UART Using Time-Division Multiplexing in FPGA CLBs

crypto-algorithms. Basic implementations of standard cryptography algorithms, like AES and SHA-1.

MiniCPU-Src. C Source Code for Minimal CPU Processor Models

6502-Code-Snippets. This repository provides snippets of 6502 code

RC4. Collection of RC4 and look-alike stream ciphers

LeastSquares. Least Squares Polynomial Fit by Cholesky Decomposition

StatisticalAnalysisTools. Statistical Analysis Tools

SMRTool. Simple Microprogram ROM (SMR) Tool Assembler/Compiler Using Python 3