JL

Expert
@Buck008

Interested in FPGA, VLSI, RISC-V, Accelerator and Digital Circuits Design.

Transformer-Accelerator-Based-on-FPGA. You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

264

zcu104_test_pl_ddr. test pl ddr；run in c++; self defined memory controller for pl ddr

4

Image-Processing-IP-Design-for-Demosaic-on-FPGA. Verilog

1

ARMv3-ISA-based-pipelined-processor. Verilog

1
4
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