Rare find

Learn Verilog. A guide to learning Verilog, the language for designing computer chips.

github.com/michaelliao/learn-verilog

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Updates

April 2025
  • sdram
  • update source
  • update half-adder
November 2022
  • fix tx-fsm
  • refactor tb
  • polish
  • rename var
  • fix tx-fsm
  • fix tb-rx-fsm
  • refactor uart: remove parity
October 2022
  • add top
  • fix bat build
  • add fsm
  • fix rs_fsm
  • export sdr_clk
  • rename
  • add sync-fifo
  • add comment
  • update key-filter
  • fix fsm