Veriloglabs. Digital circuit design exercises for students learning hardware.

github.com/chenshuo/veriloglabs
by @chenshuo

Vaya's read on this project

Problem, audience, market, and the verdict — sign in to see it.

Updates

January 2024
  • Add Reed-Solomon encoder
February 2023
  • add i2s/i2stx.sv and test bench
January 2023
  • add sha1/hmac_core.sv and test bench.
  • update aes/README.md
  • add aes/README.md
  • Add AES-128 encrypt T-box using synchronous Sbox.
  • Add AES-128 encrypt T-box using dual port memory.
  • start aes/sbox using synchronous memory.
  • Add AES-128 encrypt S-box implementation.
  • Add AES-128 encrypt T-box implementation.
December 2022
  • add sha1/sha1top.sv and testbench.
  • add sha1/sha1core.sv and testbenches.
  • add sha1block_tb.v
  • add primitive/counter.sv
  • extract sha1round from sha1block
  • add sha1block.sv
  • add sha1shift_tb.v
  • add sha1/sha1shift.v
  • Initial commit