uhdm2rtlil. Yosys SystemVerilog Parser - UHDM 2 RTLIL Yosys Pass. Highest ranking complex SystemVerilog 2 functional gate-level netlist flow for Yosys compilation

github.com/alainmarcel/uhdm2rtlil

Vaya's read on this project

Problem, audience, market, and the verdict — sign in to see it.

Updates

No recent activity.