vhdl-packet-classifier. Course Project for Digital Logic Design (CS 226), Spring 2019, IIT Bombay. Packet classifier submodule of a router implemented in VHDL and simulated in ISim using Xilinx ISE. The module supports simultaneous input and output of packets and forwards/stores packets by parsing the header for opcode and path pointer.

Problem

The full read on this project is a sign-in away — what it solves, who it serves, and where it sits in the market.

Audience

The full read on this project is a sign-in away — what it solves, who it serves, and where it sits in the market.

Market

The full read on this project is a sign-in away — what it solves, who it serves, and where it sits in the market.

Pricing

The full read on this project is a sign-in away — what it solves, who it serves, and where it sits in the market.