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xiaoan109

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ysyx-workbench. 一生一芯CPU/目前做到cache/后续主要考虑ASIC DV

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Pango-FPGA. 第七届全国大学生嵌入式芯片与系统设计竞赛FPGA创新设计赛道——紫光同创杯

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Eth_Switch_IP. 第八届集创赛中科芯杯

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rtl_design_for_interview. A repository to store basic rtl designs for interview.

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MIT-course-training. MIT6.004/MIT6.175/MIT6.375

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uart_example. Mentor APB_UART UVM Example

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AXI_XBAR_DV. AXI crossbar dv project for UVM learners.

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example_and_uvm_source_code. example code for 《UVM实战》

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