Xiongfei(Alex) GUO

luactor. A pure Lua (at least for now) Actor Model framework.

riscv-openwrt. Porting OpenWrt to RISC-V - please check https://github.com/xfguo/riscv-openwrt-port for full instructions.

tbgen. Generate testbench for your verilog module.

libubox. libubox from OpenWrt.

freescalesmartcar. 飞思卡尔智能车竞赛源代码(含记忆算法)

gitlab-commit-trello-comment. Python

riscv-openwrt-port. RISC-V OpenWrt Port

spi. SPI Master Core clone from OpenCores

gpio. GPIO IP core from opencores.

wishbone_vip. Wishbone Verification IP

skyeye. skyeye git repo clone, some modify maybe

librefpga. A libre implementation of FPGA. Written by chisel.

nirgam. a clone of "nirgam", some of my modification & improvement.

usbip. mirror of usbip on sf.net

pysnmp. pysnmp with gevent adapter (developing)

minsoc. minsoc opencores.org svn mirror

ethmac. ethmac on opencores.org

generic_fifos. generic_fifos from OpenCores/ASICS.ws

wb_mp_mem. Wishbone Multi-Ports Memory Slave Module

riscv-openwrt-linux. Openwrt favorite linux kernel version. (4.1.16)

tinyprintf. C

jtag_tap. JTAG Test Access Port from OpenCores

adv_debug_sys. Advanced Debug System by Nathan Yawn clone from OpenCores.org

uart16550. Verilog

or1200. OR1200 OpenRISC processor

ethernet_tri_mode. 10/100/1000 Mbps Tri-Mode Ethernet MAC clone from OpenCores.org

lua-daemon. A Lua C-extension for daemonizing a process.

wb_interconnect. Wishbone Interconnect Library

wb_memory. Wishbone Memory IP Library

nordb. Key-Value Database for SPI NOR Flash

rocket-chip. Rocket Chip Generator

trello-slide. 《Trello: 小团队项目管理的利器》Slide

snmp_orm. Abstraction for pysnmp

job-online. Submit Resume, Filling out Questionnaire.

vlsi-class-project. vlsi class project in Fudan Univ.

jtag_vpi. TCP/IP controlled VPI JTAG Interface.

riscv-gnu-toolchain. GNU toolchain for RISC-V, including GCC 5.3.0

home. China RISC-V User Group Website

riscv-linux. RISC-V Linux Port

riscv-openocd. Fork of OpenOCD that has RISC-V support

riscv-pk. RISC-V Proxy Kernel

Toy-Parallel-Mux-Generator. Scala

distro. Torch installation in a self-contained folder

riscv-cores-list. RISC-V Cores, SoC platforms and SoCs

asciidoctor-pdf-cjk-kai_gen_gothic. Ruby

cerbero. Cerbero build system used to build the official upstream GStreamer 1.0 SDK binaries

sifive-blocks. Common RTL blocks used in SiFive's projects

freedom. Source files for SiFive's Freedom platforms

chisel-template-w-rocket-chip. Scala

fpga-zynq. Support for Rocket Chip on Zynq FPGAs

smartsnmp. Easily writing boring SNMP MIB with Lua.

xdom_pulse_sender. Send a pulse from one domain to another timing domain.

contiki. The official git repository for Contiki, the open source OS for the Internet of Things

nanostack-1.x. from sf

wb_vip. Wishbone Verification IP

packages_10.03.1. mirror of svn://svn.openwrt.org/openwrt/branches/packages_10.03.1

odtexportplugin. odt export plugin svn clone from trac-hack