Simon Southwell

pcievhost. PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

vproc. Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus

riscV. Open source ISS and logic RISC-V 32 bit project

usbModel. USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

mem_model. High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

tcpIpPg. 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL

winfilter. WinFilter graphical FIR filter design program

sparc. Sparc version 8 Instruction Set Simulator

cpu8051. Intel(R) 8051 Instruction Set Simulator

Articles. Collected article documents in PDF covering subject with co-simulation, embedded systems, software development and logic design and verification

mico32. LatticeMico32 instruction set simulator project

eccExamples. Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material

cpu6502. A 6502 Instruction Set Simulator

rv32. An configurable open-source RISC-V instruction set simulator in C++. RV32GBC_Zicsr_Zbc_Zicntr.

jfif. JFIF and JPEG file decoder software

firfilter. Verilog finite impulse response filter

vslzw. Verilog Decoder implementing a simple LZW algorithm,

udpIpPg. 1GbE GMII UDP/IPv4 packet generator logic simulation component

lm32fpga. FPGA development board (DE1) targetted lm32 based systems design for Verilog

AXI4. AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

slzw. Simple LZW codec in C

CoSim. OSVVM submodule for Co-simulation features

pli_test. Test of VProc and mem_model PLI components in Aldec simulators

bmp. Command line bitmap manipulation utility

kernel_module. Linux Kernel Module Template

mem_subsys. Memory sub-system component project (cache/MMU)