This is your work, valued

Stefan Wallentowitz

Elite
@wallento

wavedrompy. WaveDrom compatible python command line

118

riscv-python-model. Python Model of the RISC-V ISA

62

magenta. Magenta Microkernel

23

cocotbext-wishbone. Python

22

wb2axi. Wishbone to ARM AMBA 4 AXI

17

or1200mp. Multiprocessor variant of OpenRISC 1200 processor

12

cocotbext-uart. UART cocotb module

11

riscv-cocotb. cocotb infrastructure for RISC-V core testing

10

riscv-ca-teaching. RISC-V in Practical Computer Architecture Education

9

sungrow-websocket. Python Library to acees the websocket interface of Sungrow inverters

9

uartdpi. UART DPI module

7

uart16550. Fork from OpenCores UART 16550

7

pipeline-viewer. CPU Pipeline Viewer

7

board_armjtag_pmod_compatible. Connector board (ARM) JTAG, Pmod compatible

4

pmod_switchbox. Pmod Switchbox

3

mooreandmore. Data to print Moore's law

3

rust-crash-course-jupyter-notebooks. A series of Jupyter notebooks to learn the basics of Rust!

2

Cores-SweRV-EL2. SystemVerilog

2

serv. SERV - The SErial RISC-V CPU

2

core_usb_cdc. Basic USB-CDC device core (Verilog)

2

openlane-examples. Examples from the Openlane repository, adapted as Fusesoc cores

2

OpenLane. OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

2

bbb-scrape. Scrape Big Blue Button

2

riscv. SystemVerilog

2

educational-materials. Educational materials for RISC-V

2

ariane. Ariane is a 6-stage RISC-V CPU capable of booting Linux

1

riscv-card. An unofficial reference sheet for RISC-V, the free and libre ISA from UC Berkeley.

1

systemcmd5. SystemC/Verilog MD5

1

rv8-io.github.io. RISC-V simulator for x86-64

1

riscv-isa-sim. Spike, a RISC-V ISA Simulator

1

opensource-design-verification-workshop. Open Source Design Verification Workshop

1

tt09-4bit-toycpu. 4-bit Toy CPU

1

ibex. Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

1

home-assistant.io. :blue_book: Home Assistant User documentation

1

scr1. SCR1 is a high-quality open-source RISC-V MCU core in Verilog

1

esp-idf. Espressif IoT Development Framework. Official development framework for Espressif SoCs.

1

verilator. Verilator open-source SystemVerilog simulator and lint system

1

subservient. Small SERV-based SoC primarily for OpenMPW tapeout

1

riscv-boom. BOOM: Berkeley Out-of-Order Machine

1

rv8. RISC-V simulator for x86-64

1

fossi-research.

1

opentitan. OpenTitan: Open source silicon root of trust

1

CircuitVerse. CircuitVerse Primary Code Base

1

lowrisc-nexys4. FPGA demo for Digilent NEXYS 4 board

1

fusesoc. Python

1

mgpio. Multi-bank General Purpose I/O

1

fusesoc_cores. SystemVerilog

1

binutils-gdb. Binutils mirror

1

orpsoc-cores. Core description files for ORPSoCv3

1

sandbox-verilator-action. Verilog

1

fusesoc-templates-demo. Demo files for FuseSoC templates

1

lowrisc-fpga. Untethered (stand-alone) FPGA implementation of the lowRISC SoC

1

barista. Barista platform information module for embedded systems

1