VSD

vsdsram_sky130. SourcePawn

vsdStdCellCharacterizer_sky130. Python

vsdflow. VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).

avsddac_3v3_sky130_v2.

rvmyth_avsddac_interface. Verilog

vsdsram. An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop) to store each bit. The size of SRAM specs is 32kbit/4k bytes with 1.8v. A 6T SRAM pairs up with two access transistors for read, write state and cross coupled inverter to hold/regenerate the state.

avsddac_3v3_sky130_v1. Verilog

vsdfpga_labs. C

avsdbgp_3v3_sky130_v1. PostScript

vsdopen2021_bgr. SourcePawn

IndiaRiscvTapeoutProgram. This repo is for users to raise any queries related to the program

rvmyth_avsdpll_interface. Verilog

avsdcmp_3v3_sky130.

VSDBabySoC. Verilog

vsdsquadron. Python

avsdbgp_3v3_sky130_v2. Verilog

RISC-V-MYTH-Workshop. Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for Me in Thirty Hours" Workshop

avsdpll_1v8_sky130_ss.

vsdsquadron_pio. Python

VSDMemSoC. Verilog

avsdbgp_3v3. avsdbdg_3v3 is a Bandgap Reference circuit, which is used to generate a constant voltage reference in analog domain which is independent of temperature and supply voltage variations.

vsdRiscvScl180. Verilog

VSD-IAT-Workshop-Github-Repos. GitHub is the new Resume for VLSI industry GitHub is indeed the new RESUME for VLSI industry. Really, if you are recruiting person and looking forward to judge a new candidate for a role in company, ask for GitHub project link. Projects written on resume and projects available on GitHub by a candidate will immediately give you an idea about his/her perseverance, dedication, sincerity, productivity and amount of hard-work he/she can put inside a project.

avsdadc_sky130.

vsdStdCellList_sky130.

vsdmixedsignalflow. This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.

vsdcontainer. Tcl

skywater-pdk. Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

avsddac_3v3. SourcePawn

avsdmux4x1_3v3. Shell

vsdscl180. Verilog

avsdmux2x1_3v3. Shell

vsdbbcud4f. SourcePawn

shakti_vsdfpga. Verilog

vsdospowercalc. Python

vsd_pv_synp_40nm.