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i2s. i2s core, with support for both transmit and receive
33wb_sdram_ctrl. SDRAM controller with multiple wishbone slave ports
30ar100-info. C
13llvm-or1k. LLVM backend for OpenRISC 1000
12diila. A Device Independent Integrated Logic Analyzer
12clang-or1k. Clang for OpenRISC 1000
7compiler-rt-or1k. "compiler-rt" Runtime Library with OpenRISC 1000 support
4minimig-de1. Minimig for the DE1 board
4or1k-src. OpenRISC 1000 port for sourceware.org's src tree (binutils, gdb, newlib, etc.)
3scummvm. ScummVM main repository
3eco32-linux. Linux port for the ECO32 architecture.
2eco32-sim. Functional simulator for eco32, from http://opencores.org/project,eco32
2or1k-gcc. C
2mor1kx-dev-env. Development and verification environment for the mor1kx core
2musl-cross. A small suite of scripts and patches for building musl libc cross compilers.
1grabber. Redirects stdin to stdout while grabbing mouse/keyboard input
1eco32f. Pipelined version of the eco32 CPU architecture implemented in verilog
1sublime. Subtractive synthesizer core
1eco32-gcc. gcc backend for eco32. "Forked" from https://codeinbarrels.net/jens/egg/src/egg-0.0.5.tar.bz2 and updated to gcc 4.8.1
1uClibc-or1k. uClibc for OpenRISC 1000
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