Joachim Strömbergson

aes. Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

sha256. Hardware implementation of the SHA-256 cryptographic hash function

trng. True Random Number Generator core implemented in Verilog.

sha1. Verilog implementation of the SHA-1 cryptgraphic hash function

sha512. Verilog implementation of the SHA-512 hash function.

chacha. Verilog 2001 implementation of the ChaCha stream cipher.

blake2. Hardware implementation of the blake2 hash function

sha3. FIPS 202 compliant SHA-3 core in Verilog

blake2s. Verilog implementation of the 32-bit version of the Blake2 hash function

siphash. Hardware implementation of the SipHash short-inout PRF

modexp. Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.

cmac. Implementation of the CMAC keyed hash function using AES as block cipher.

ChaCha20-Poly1305. Hardware implementation of the ChaCha20-Poly1305 AEAD construction

prince. The Prince lightweight block cipher in Verilog.

poly1305. Hardware implementation of the poly1305 message authentication function.

chacha_testvectors. Generator and Internet Draft (I-D) documenting test vectors for the stream cipher ChaCha.

md5. Hardware implementation of the hash function md5

ascon. Verilog implementation of the ASCON lightweight authenticated encryption and hashing algorithm

gift. Hardware implementation of the GIFT-128 lightweight block cipher

ed25519. ed25519 public key signature implemented in Verilog.

cbc. CBC block cipher mode of operation for AES.

6502. Verilog implementation of a MOS6502 compatible CPU core.

uart. A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.

rosc_entropy. Entropy source based on jitter between multiple, digital ring oscillators.

aes_mask. Experimental core for performing masking of AES by generating noise.

figaro. Implementation of the FiGaRO TRNG for FPGAs

gcm. Galois Couter Mode implementation in Verilog.

grain128. Hardware implementation of the Grain128AEAD stream cipher

verilator_template. (Hopefully) simple template for a Verilator SystemVerilog project with a usable testbench

awesome-opensource-hardware. List of awesome open source hardware tools, generators, and reusable designs

snow5. Hardware implementation of the SNOW-V stream cipher.

curve25519. Verilog 2001 of the Curve25519 elliptic curve based function.

aes_6502. My attempt at making a fast AES-128 implementation on MOS 6502

hmac. HMAC-SHA-256 in Verilog 2001

avalanche_entropy. Entropy collector and provider for an external avalanche noise based entropy source.

xtea. Verilog implementation of the xtea block cipher

rc4. An experimental RC4 hardware implementation with one cycle/iteration performance.

salsa20. Sals20 Stream Cipher core in Verilog

ccm. ccm mode hardware implementation

view_rnd. A simple program for viewing random values as an image.

vga. vga

Practical-Cryptography-for-Developers-Book. Practical Cryptography for Developers: Hashes, MAC, Key Derivation, DHKE, Symmetric and Asymmetric Ciphers, Public Key Cryptosystems, RSA, Elliptic Curves, ECC, secp256k1, ECDH, ECIES, Digital Signatures, ECDSA, EdDSA

ice40_ultraplus_examples. Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

fpga_eth_filter. FPGA based Ethernet traffic filter and manipulator for the TerasIC ETHERNET-HSMC Card

tracegen. A tool for generating synthetic traces with side-channel leakage.

r5. A simple Verilog implementation of RISC-V.

extract_ev_data. Pure Python program used to extract EV data from Mozilla CA roots. Used to generate EV validation data in sslyze.

hc. Hardware implementation of the HC stream cipher.

bigmath. Project for testing and developing HW-implementations of integer operations. mult, mod, add, div etc.

pyat88ck590. Python program to talk to the Atmel AT88CK590 Crypto Authentication Evaulation Kit.

Tweetnacl. Python implementation of the TweetNaCl cryptograhic library

aead_aes_siv_cmac. Hardware implementation of the AEAD_AES_SIV_CMAC

chaskey. Verilog implementation of the Chaskey lightweight message authentication code (MAC) function.

rc4_6502. MOS 6502 implementation of the old RC4 stream cipher. Yes, it is broken.

fusesoc. Package manager and build abstraction tool for FPGA/ASIC development

aes-min. Minimal AES-128 encryption. Suitable for small embedded systems. Including an on-the-fly key schedule variant for minimal RAM usage.

blake3. Hardware implementation of the Blake3 hash function

ca_prng. Cellular Automata based PRNG

fltfpga. FairLight FPGA demo board based on TerasIC G5C

advent_of_code_2019. Solutions to Adevent of Code 2019