This is your work, valued

Santa Clara, CA

Matthew L Morra

Intermediate
@oz-matt

Axi-Lite-SVA. Assertion property files for axi lite slaves/masters

6

cdr_rnm. sv-rnm behavioral sim of a pcie cdr

3

ozphy_uvm. SystemVerilog

2

PLayouts. PADS Layout files for all PCBs

2

CScope. C++

2

EasierUVM-SimpRisc-ws. Verification suite of the SimpRisc CPU using the EasierUVM code gen

1

UVM-simprisc-ws. UVM testing suite for the SimpRisc CPU

1

AdvFxsDSP. Creating blocks for Blackfin ADSP-537

1

ozphy. SystemVerilog

1

cpll_ams. Verilog-AMS verification of CPLL

1

serum. SystemVerilog

1

AquaManager-Desktop.

1