Kamyar Mohajerani

ORCA-risc-v. RISC-V by VectorBlox

krystals. Rust implementation of CRYSTALS post-quantum cryptography primitives: Kyber key-encapsulation mechanism and Dilitium digital signature algorithms

kyber.light. Light-weight Hardware Implementation of CRYSTALS Kyber PQC

chisel-arithmetics. Implementation of low-level hardware arithmatic operations in Chisel

bluelight. Hardware implementation of Lightweight Cryptography candidates in Bluespec SystemVerilog.

scasim. Simulation-based Side-channel Evaluation

dslx-vscode. XLS DSLX Language Support for Visual Studio Code

circt-rs. Rust bindings for MLIR CIRCT

wavedrom. :ocean: Digital timing diagram in your browser

pulsar. Cache Timing Side-channel Attacks in Rust

rocc-template. Scala

ghdl-yosys-plugin. VHDL synthesis (based on ghdl)

lefdef. LEF/DEF 5.8_60p009 from Si2 OpenAccess https://si2.org/oa-tools-utils-libs/

spike-uart. UART device plugin for riscv-isa-sim (a.k.a Spike)

verilator. Verilator open-source SystemVerilog simulator and lint system

picorv32. PicoRV32 - A Size-Optimized RISC-V CPU

cvcx. CVCx is a fork of OSS CVC from Tachyon DA

hal. HAL – The Hardware Analyzer

Xoodoo. VHDL

litex-boards. LiteX boards files

core-v-xif. SystemVerilog

Algorithm-Design-Manual-Programs-V3. Programs for the third edition of the Algorithm Design Manual

cocolight. Lightweight cocotb verification library

pqcrypto. Rust Post-Quantum cryptography

systemc. Core SystemC Library

pyHDLParser. Simple Python parser for extracting HDL (VHDL or Verilog) documentation

masq. Verilog

ultra96v2_imx219_to_displayport. Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL

symbolator. Generate symbols from HDL components/modules

SILVER. SILVER - Statistical Independence and Leakage Verification

yosys-f4pga-plugins. Plugins for Yosys developed as part of the SymbiFlow project.

sparkle. Verilog

vscode-verilog-hdl-support. Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

riscv-coremark. Setup scripts and files needed to compile CoreMark on RISC-V

projf-explore. Project F brings FPGAs to life with exciting open-source designs you can build on.

cudd-orig. CUDD: CU Decision Diagram is a package for the manipulation of Binary Decision Diagrams (BDDs), Algebraic Decision Diagrams (ADDs) and Zero-suppressed Binary Decision Diagrams (ZDDs)

ChiselEnvironment. Where you build your ChiselDSP project

OpenDB. Database and Tool Framework for EDA

pyVhdl2Sch. pyVhdl2sch is b Python based VHDL to (pdf) schematic converter

lwc_candidates. Hardware implementations of NIST LWC candidates from VT and GMU supporting GMU LWC Hardware API

LWC. Development Package for the Hardware API for Lightweight Cryptography

freepdk-45nm. ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

basejump_stl. BaseJump STL: A Standard Template Library for SystemVerilog

opengg. OpenGL-like graphics pipeline on a Xilinx FPGA

Elephant. VHDL

oh. Open Hardware (OH!) Library for FPGAs and ASICs

ghdl. VHDL 2008/93/87 simulator

hammer. HAMMER: Highly Agile Masks Made Effortlessly from RTL

zturn-stuff. Various files for the MYiR Z-turn Boards (Z7010 & Z7020)

flopoco. A fork of FloPoCo http://flopoco.gforge.inria.fr/

ZYNQ-Cookbook. This is a wiki and code sharing for ZYNQ

wavedrom-editor. NWJS App https://wavedrom.com/editor.html

wavedrom-edit.

gtkwave3-gtk3. gtkwave3-gtk3 git mirror (macOS, no X11)

vivado. Shell

spoc_lwc. Spoc AEAD with PW=SW=32 bits using LWC API

comet_cham_lwc_v2. COMET AEAD with CHAM primitive, PW=32=32 using LWC API (Improved v2)

Flute. RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance