Kevin Laeufer

wellen. wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.

rfuzz. rfuzz: coverage-directed fuzzing for RTL research platform

rtl-repair. Fast Symbolic Repair of Hardware Design Code

rtl-fuzz-lab. A Modular Open-Source Hardware Fuzzing Framework

pynq. PYNQ with Chisel and Rust

simulator-independent-coverage. Project Repo for the Simulator Independent Coverage Research

fst-reader. Native Rust implementation of the FST waveform format from GTKWave.

icesugar-chisel. Chisel Examples for the iCESugar FPGA Board

open-source-formal-verification-for-chisel. Jupyter Notebook

paso. A Chisel Integrated Specification and Verification Language.

comparing-random-testing-and-bmc. Verilog

picojava2-archive. PicoJava2 RTL sources which are published under the Sun Community Source License, which is NOT a Open Source license.

chisel-sequences. sequence prototype

custom-afl-instrumentation. A small example on how to use a custom coverage/progress metric for AFL. Based on the llvm_mode from AFL.

spec-impl. Scala

transactional-verification-with-protocols. Contains a prototype implementation of a transactional verification algorithm that uses protocols to connect functional model and implementation.

kiwi-formal. Experimental (formal) verification library for Chisel.

serv-chisel. reimplementation of the serv core in Chisel (https://github.com/olofk/serv)

darjeeling-jvm. git import of the embedded jvm from Delft University of Technology http://darjeeling.sourceforge.net

cs267-tutorials. Materials to help you with the cs267 homework.

chisel-verification-examples. Scala

stm32f3-minimal-cdc. a minimal usb cdc loopback implementation for the stm32f3 discovery board using xpcc

guarded_atomic_actions. Scala

components-next. Some experiments with loosely coupled components on microcontrollers.

utest-rs. an effort to develop a testing solution for rust on deeply embedded, bare metal targets

fst-writer. Rust library for writing waveform traces in the FST format.

ucta. micro controller trace analysis

essent. high-performance RTL simulator

etm-test. Playing around with the micro controller execution tracing.

xpcc-swd. port of scanlime's SWD code for the esp8266 to xpcc

firrtl2. UC Berkeley Copy of the FIRRTL Compiler

hwmcc20. Hardware Model Checking Competition 2020 Benchmarks and Results

hardware-bugbase. SystemVerilog

undergrad-exercises. Some exercises for undergraduates that work on research with me.

cpp-debugging-interactive-unit. Interactive instructional unit created as the course project for SCMATHE 220C at UC Berkeley.

AFL. american fuzzy lop - a security-oriented fuzzer

firesim. FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

ip-contributions. For contributions of Chisel IP to the chisel community.

jade-mirror. unofficial git mirror of http://jade.tilab.com/developers/source-repository/