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SimpleTPU. A FPGA Based CNN accelerator, following Google's TPU V1.
176LDPCC. Low Density Parity Check codes encoder and decoder, in particular for CCSDS standards.
68hls_ldpc_dec. Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
45Viterbi-decoder. convolution codes simulation, decoder using the viterbi algorithm.
11fpga_hls_program.
3fpga_parallel_computing. Parallel computing methods in FPGA using HLS
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