brabect1

sta_basics_course. Introductory course into static timing analysis (STA).

zr-soc. RISC-V SoC featuring zero-riscy core.

hdl_api_doc_test. Test repository of some API Doc generators for SystemVerilog.

sv_handshake_comps. Reusable handshake components in SystemVerilog.

e200_opensource. The Ultra-Low Power RISC Core

riscv_jtag_dm. RISC-V Debug Mocule with JTAG Transport.

risc8. Derivative version of the free risc8 micro core originally by Tom Coonan.

f4pga-sdf-timing. Python library for working Standard Delay Format (SDF) Timing Annotation files.

ipxact-manifest-utils. Python3 scripts to compile IP-XACT 2014 based manifest files.

Continued_Logarithm_Arithmetic. Hosts publications and data of PhD thesis in Continued Logarithm Arithmetic.