Cheng Liu

cycle-accurate-SystemC-simulator-over-ramulator. An example of using Ramulator as memory model in a cycle-accurate SystemC Design

graph-database-accel-survey. TeX

graph_accelerator. Graph accelerator on FPGAs and ASICs

bfs-using-vivado-hls. BFS design and optimization using Vivado HLS in SDAccel.

QuickDough. Source code, benchmarks, etc.

doc. My papers, reports, etc.

pagerank. Add a vertex based page rank computing model

bfs_with_Intel_OpenCL. OBFS: OpenCL based BFS optimizations on Intel Xeon-FPGA (Harp v2)

liu-cheng.github.io. Homepage of Cheng Liu, Insititute of Computing Technology, Chiense Academy of Scinces

ChipPilot. LLM based intelligent IC design toolbox.